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1 ?2017 integrated device technology, inc. february 14, 2017 description the 8S89296 is a high performance lvds programmable delay line. the delay can vary from 2.2ns to 12.5ns in 10ps steps. the 8S89296 is characterized to operate from a 2.5v power supply and is guaranteed over industrial temperature range. the delay of the device varies in discrete steps based on a control word. a 10-bit long control word sets the delay in 10ps increments. also, the input pins in and nin default to an equivalent low state when left floating. the control register can accept cmos or ttl level signals. features ? one lvds level output ? one differential clock input pair ? differential input clock (in, nin) can accept the following signaling levels: lvpecl, lvds, cml ? maximum frequency: 800mhz ? programmable delay range: 2.2ns to 12.5ns in 10ps steps ? d[10:0] can accept lvpecl, lvcmos or lvttl levels ? full 2.5v supply voltages ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package block diagram figure 1: block diagram q nq 0 1 512 gd 0 1 256 gd 0 1 128 gd 0 1 64 gd 0 1 32 gd 0 1 16 gd 0 1 8 gd 0 1 4 gd 0 1 2 gd 1 gd in nin gd = gate delay 0 1 1 gd 10-bit latch d[9:0] len setmin setmax latch d[10] len cascade ncascade vbb vcf vef nen 0 1 ftune transistor count: 8686 8S89296 datasheet lvds programmable delay line
2 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet pin assignments figure 2: pin assignments for 5mm x 5mm 32-lead package pin description and pin characteristic tables table 1: pin descriptions number name type [a] description 1 d8 input (pd) parallel data input d8. single-ended lvcmos, lvttl, lvpecl interface levels. 2 d9 input (pd) parallel data input d9. single-ended lvcmos, lvttl, lvpecl interface levels. 3 d10 input (pd) parallel data input d10. single-ended lvcmos, lvttl, lvpecl interface levels. 4 in input (pd) non-inverting differential input. 5 nin input (pu/ pd) inverting differential input. 6v bb output reference voltage output. this pin can be used to re-bias ac-coupled inputs to in and nin. when used, de-couple to v dd using a 0.01 ? f capacitor. if not used, leave floating. 7v ef output reference voltage output. see table 4 . 8v cf input reference voltage input. the voltage driven on v cf sets the logic transition threshold for d[10:0]. 9 gnd power power supply ground. 10 len input (pd) d inputs load and hold control input. when high, latches the d[10:0] bits. when low, the d[10:0] latches are transparent. single-ended lvpecl interface levels. see table 3 . 8S89296 d7 d6 d2 d1 gnd d3 d5 d4 v cf v ef v bb nin in d10 d9 d8 gnd len setmin setmax v dd ncascade cascade nen 910111213141516 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 f tune v dd v dd nq q v dd d0 gnd 24 23 22 21 20 19 18 17
3 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet 11 setmin input (pd) minimum delay set logic input. when high, d[10:0] registers are reset. when low, the delay is set by setmax or d[10:0]. default is low when left floating. single-ended lvpecl interface levels. see table 5 . 12 setmax input (pd) maximum delay set logic input. when setmax is set high and setmin is set low, d[10:0] = 1111111111. when setmax is low, the delay is set by setmin or d[10:0]. default is low when left floating. single-ended lvpecl interface levels. see table 5 . 13 v dd power positive supply pin. 14 ncascade output lvds inverted output. 15 cascade output lvds non-inverted output. 16 nen input (pd) single-ended control enable pin. when low, q is delayed from in. when high, q is a differential low. default is low when left floating. single-ended lvpecl interface levels. see table 2 . 17 f tune analog input fine tune delay control input. by varying the input voltage, it provides an additional delay. 18 v dd power positive supply pin. 19 v dd power positive supply pin. 20 nq output differential output pair. lvds interface levels. 21 q output differential output pair. lvds interface levels. 22 v dd power positive supply pin. 23 d0 input (pd) parallel data input d0. single-ended lvcmos, lvttl, lvpecl interface levels. 24 gnd power power supply ground. 25 d1 input (pd) parallel data input d1. single-ended lvcmos, lvttl, lvpecl interface levels. 26 d2 input (pd) parallel data input d2. single-ended lvcmos, lvttl, lvpecl interface levels. 27 d3 input (pd) parallel data input d3. single-ended lvcmos, lvttl, lvpecl interface levels. 28 gnd power power supply ground. 29 d4 input (pd) parallel data input d4. single-ended lvcmos, lvttl, lvpecl interface levels. 30 d5 input (pd) parallel data input d5. single-ended lvcmos, lvttl, lvpecl interface levels. 31 d6 input (pd) parallel data input d6. single-ended lvcmos, lvttl, lvpecl interface levels. 32 d7 input (pd) parallel data input d7. single-ended lvcmos, lvttl, lvpecl interface levels. a. pull-up (pu) and pull-down (pd) resistors are indicated in parentheses. pullup and pulldown refer to internal input resistors. see table 7 , pin characteristics, for typical values. table 1: pin descriptions number name type [a] description
4 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet figure 3: propagation delay vs. f tune voltage graph function tables table 2: delay enable nen q, nq 0 (default) in, nin delayed 1q = low, nq = high table 3: digital control latch len latch action 0 (default) pass through d[10:0] 1 latched d[10:0] table 4: v cf connection for d[10:0] logic interface input v cf connection d[10:0] logic interface v cf v ef [a] a. connect v cf (pin 8) to v ef (pin 7). lvpecl v cf no connect lvcmos v cf 1.5v source lvttl \ 10 0 10 20 30 40 50 60 70 00.511.522.5 \ 40c 25c 85c f tune voltage (v) propagation delay (ps)
5 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet table 5: theoretical delta delay values [a] a. refer to table 13 , ac characteristics , for typical step delay values. d[9:0] value setmin setmax programmable delay [b] (ps) b. inherent propagation delay not included. propagation delay = inherent propagation delay ? programmable delay. inherent propagation delay equals the propagation delay with the programmable delay = 0ps. xxxxxxxxxx h l 0 0000000000 l l 0 (default) 0000000001 l l 10 0000000010 l l 20 0000000011 l l 30 0000000100 l l 40 0000000101 l l 50 0000000110 l l 60 0000000111 l l 70 0000001000 l l 80 0000010000 l l 160 0000100000 l l 320 0001000000 l l 640 0010000000 l l 1280 0100000000 l l 2560 1000000000 l l 5120 1111111111 l l 10230 xxxxxxxxxx l h 10240
6 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet absolute maximum ratings the absolute maximum ratings are stress ratings only. stresses greater than those listed below can cause permanent damage to th e device. functional operation of the 8S89296 at absolute maximum ratings is not implied. exposure to absolute maximum rating conditions may affect device reliability. dc electrical characteristics table 6: absolute maximum ratings table item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd ? 0.5v outputs, i o (lvds) continuous current surge current 10ma 15ma junction temperature, t j 125 ? c storage temperature, t stg -65 ? c to 150 ? c table 7: dc input characteristics symbol parameter test conditions minimum typical maximum units c in input capacitance 2 pf r pullup input pull-up resistor 50 k ? r pulldown input pull-down resistor 50 k ? table 8: power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v i dd power supply current no load, maximum v dd 158 ma table 9: lvcmos/lvttl dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage 1.7 v dd ? 0.3 v v il input low voltage -0.3 0.7 v i ih input high current d[10:0] v dd = v in = 2.625v 150 a i il input low current d[10:0] v dd = 2.625v, v in = 0v -10 a
7 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet table 10: lvpecl differential dc characteristics, v dd = 2.5v 5%, gnd = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units i ih input high current in, nin v dd = v in = 2.625v 150 a i il input low current in v dd = 2.625v, v in = 0v -10 a nin v dd = 2.625v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode range [a] gnd ? 0.95 v dd v v bb output voltage reference i bb = ? 150a v dd ? 1.55 v dd ? 1.35 v dd ? 1.15 v v ef mode connection i ef = ? 150a v dd ? 1.55 v dd ? 1.35 v dd ? 1.15 v a. common mode input voltage is defined as v ih. table 11: lvpecl single-ended dc characteristics, v dd = 2.5v 5%, gnd = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage [a] a. to enable lvpecl interface levels on pins d[10:0], pin 7 must be connected to pin 8. see table 4 . d[10:0], len, nen, setmin, setmax v dd ? 1.2 v dd ? 0.940 v v il input low voltage [a] d[10:0], len, nen, setmin, setmax v dd ? 1.870 v dd ? 1.45 v i ih input high current d[10:0], len, nen, setmin, setmax v dd = v in = 2.625v 150 a i il input low current d[10:0], len, nen, setmin, setmax v dd = 2.625v, v in = 0v -10 a table 12: lvds dc ch aracteristics, v dd = 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v od differential output voltage 350 650 mv ? v od v od magnitude change 50 mv v os offset voltage 1.10 1.30 v ? v os v os magnitude change 50 mv
8 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet ac electrical characteristics table 13: ac characteristics, v dd = 2.5v 5%, t a = -40c to 85c [a], [b] a. characterized up to f out = 800mhz unless noted otherwise. b. electrical parameters are guaranteed over the specified ambient operating temperatur e range, which is established when the devi ce is mounted in a test socket with maintained transverse airflow greater than 500lfpm. the device will meet specifications after the rmal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units f out output frequency q, nq output 800 mhz t pd propagation delay in to q, nq dx = 0 1700 2200 2700 ps in to q, nq dx = 1023 9500 12500 15000 ps nen to q, nq dx = 0 1700 2400 3200 ps t pd_range programmable propagation range t pd_max ? t pd_min 8000 ps ? t step delay d0 = high 15 ps d1 = high 25 ps d2 = high 45 ps d3 = high 85 ps d4 = high 165 ps d5 = high 330 ps d6 = high 645 ps d7 = high 1270 ps d8 = high 2540 ps d9 = high 5075 ps d[9:0] = high 10135 ps inl integral non-linearity [c] c. deviation from a linear delay (actual min. to max.) in the 1024 programmable steps. 10 ps t s setup time d to len -20 ps d to in, nin -80 ps nen to in, in -35 ps t h hold time len to d -175 ps in, nin to nen -575 ps t r release time nen to in, nin 250 ps setmax to len 225 ps setmin to len 240 ps t r / t f output rise/fall time q, nq 20% to 80% at 100mhz 70 300 ps odc output duty cycle 40 60 %
9 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet applications information recommendations for unused input pins inputs: lvcmos control pins all control pins have internal pulldown resistors; additional resistance is not required but can be added for additional protec tion. a 1k ? resistor can be used. wiring the differential input to accept single-ended levels figure 4 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be lo cated as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the inpu t will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impeda nce. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even thou gh the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specif ies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larg er, however v il cannot be less than -0.3v and v ih cannot be more than v dd ? 0.3v. suggest edge rate faster than 1v/ns. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datashe et specifications are characterized and guaranteed by using a differential signal. figure 4: recommended schematic for wiring a differential input to accept single-ended levels
10 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet 2.5v lvpecl clock input interface the in/nin accepts lvpecl, lvds, cml and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figure 5 to figure 9 s how interface examples for the in/nin input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult wi th the vendor of the driver component to confirm the driver termination requirements. figure 5. in/nin input driven by a cml driver figure 6. on/nin input driven by a 2.5v lvpecl driver figure 7. in/nin input driven by a 2.5v lvds driver figure 8. in/nin input driven by a built-in pullup cml driver figure 9. in/nin input driven by a 2.5v lvpecl driver with ac couple in nin cml 2.5v zo = 50 zo = 50 2.5v 2.5v r1 50 r2 50 lvpecl differential inputs r3 125 r4 125 r1 84 r2 84 2.5v zo = 50 zo = 50 in nin 2.5v 2.5v lvpecl lvpecl differential inputs in nin v bb 2.5v r1 1k r2 1k 2.5v zo = 50 zo = 50 c1 c2 r5 100 lvds c3 0.1f lvpecl differenti al inputs 2.5v r1 100 cml built-in pullup in nin 2.5v zo = 50 zo = 50 lvpecl differenti al inputs r1 50 r2 50 r5 100 - 200 r6 100 - 200 in v bb nin 2.5v lvpecl 2.5v zo = 50 zo = 50 2.5v lvpecl differenti al inputs c1 c2
11 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorpora ted on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 10 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board thro ugh a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern m ust be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application sp ecific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical anal ysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid an y solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recom mendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead-frame base package, amkor technology. figure 10: p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
12 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds co mpliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 11 can be used with either type of output structure. figure 12 , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termina tion, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since the se outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the outpu t. figure 11: standard lvds termination figure 12: optional lvds termination lvds driver z o ? z t z t lvds receiver lvds driver z o ? z t lvds receiver c z t 2 z t 2
13 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet power considerations this section provides information on power dissipation and junction temperature for the 8S89296. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8S89296 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 2.5v ? 0.125v = 2.625v, which gives worst case results. the maximum current at -40c is as follows: i dd_max = 158ma ? power_ max = v dd_max ? i dd_max = 2.625v ? 158ma = 415mw the maximum current at 85c is as follows: i dd_max = 150ma power_ max = v dd_max ? i dd_max = 2.625v ? 150ma = 394mw 2. junction temperature. junction temperature, t j , is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for t j is as follows: tj = ? ja ? pd_total ? t a t j = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 39.5c/w per table 14 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c ? 0.394w ? 39.5c/w = 100.6c. this is below the limit of 125c. this calculation is only an example. t j will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 14: thermal resistance ? ja for 32 lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 39.5c/w 34.5c/w 31.0c/w
14 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet package outline and package dimensions figure 13: 32-lead vfqfn package
15 ?2017 integrated device technology, inc. february 14, 2017 8S89296 datasheet package outline and package dimensions, continued figure 14: 32-lead vfqfn package
8S89296 datasheet 16 ?2017 integrated device technology, inc february 14, 2017 disclaimer integrated device te chnology, inc. (idt) and its aff iliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specific ations described herein at any time, without notice, at idt?s sole discretion. performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. the informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of idt's products for any particular purpose, an implied warran ty of merchantab ility, or non-infringement of the intellectual p roperty rights of others. this documen t is presented only as a guide and does not convey any license under intellectual propert y rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other c ountries. other trademarks used herein are the property of idt or their respective third party owners. for datas heet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology , inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com marking diagram ordering information revision history part/order number marking package shipping packaging temperature 8S89296nlgi idt8S89296nlgi 32 lead vfqfn, lead-free tray -40 ? c to ? 85 ? c 8S89296nlgi8 idt8S89296nlgi 32 lead vfqfn, lead-free tape & reel -40 ? c to ? 85 ? c revision date description of change february 14, 2017 initial datasheet. 1. line 1 idt is the part number prefix. 2. line 2 is the part number. 3. line 3 is the package code. 4. line 4: # denotes stepping. ?yww? is the last digit of the year and week that the part was assembled. ?$? denotes mark code.

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